A 0.65--1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter
نویسندگان
چکیده
منابع مشابه
A 0.65–1.35 GHz synthesizable all-digital phase locked loop with quantization noise suppressing time-to-digital converter
This paper presents a new quantization noise suppression method for a time-to-digital converter (TDC) and proposes an all-digital phase-locked loop (ADPLL) architecture using only standard cell logic gates. Using a new multiple input multiple output (MIMO) quantization noise suppression method provides an order of √ 2N improvement in TDC resolution with N parallel TDC channels. Suppressed noise...
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Acknowledgement It has been a real privilege and honor to be a graduate student in joint master program of micro-electronic department at Fudan University and SoC program of Royal Institute of Technology (KTH). It is definitely an enjoyable and unforgettable experience to work with many brilliant students and teachers across country borders. I am deeply indebted to many people who have assisted...
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for their valuable guidance over the course of the last two years. I would also like to thank members of my thesis committee for their useful feedback. Thanks to Pavan Hanumolu and Gil-Cho Ahn for always being supportive and providing helpful insight into design issues. Thanks to everyone else in lab for being open to answering questions and putting up with me during soccer. Thanks to AFRL for ...
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ژورنال
عنوان ژورنال: TURKISH JOURNAL OF ELECTRICAL ENGINEERING & COMPUTER SCIENCES
سال: 2017
ISSN: 1300-0632,1303-6203
DOI: 10.3906/elk-1601-185